Transcription of ECEN720: High-Speed Links Circuits and Systems Spring 2021
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ECEN720: High-Speed Links Circuits and Systems Spring 2021
Sam PalermoAnalog & Mixed-Signal CenterTexas A&M UniversityECEN720: High-Speed Links Circuits and SystemsSpring 2021 Lecture 12: CDRsAnnouncements Lab 6 due Apr 12 Project Preliminary Report due Apr 19 Project Final Report due Apr 292 Agenda CDR overview CDR phase detectors Single-loop analog PLL-based CDR Dual-loop CDRs Phase interpolators CDR jitter properties3 Embedded Clock I/O Circuits4 TX PLL TX Clock Distribution CDR Per-channel PLL-based Dual-loop w/ Global PLL & Local DLL/PI Local Phase-Rotator PLLs Global PLL requires RX clock distribution to individual channelsClock and Data Recovery A clock and data recovery system (CDR) produces the clocks to sample incoming data The clock(s)
• Comparing the current sample versus the desired reference level (e n) and correlating that with the appropriate data ... • Final performance verification should be done with a time-domain non-linear model [Lee] ... Calibration Data CLK Edge CLK 4 4 4 4 VCNT 14 GHz LC-VCO. 56Gb/s PAM4 Analog PLL-based CDR 25 • LC-VCO w/
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