Transcription of Evaluating the HMC7044 Dual Loop Clock Jitter Cleaner
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Evaluating the HMC7044 Dual Loop Clock Jitter Cleaner
EK1 HMC7044LP10B User GuideUG-826 One Technology Way P. O . Box 9106 Norwood, MA 02062-9106, Te l : Fax: Evaluating the HMC7044 dual Loop Clock Jitter Cleaner PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 10 FEATURES Simple power connection using USB connection and on-board LDO voltage regulators LDOs can be bypassed for power measurements AC-coupled differential SMA connectors SMA connectors for 2 reference Inputs 6 Clock outputs 1 VCXO output Microsoft Windows based evaluation software with simple graphical user interface On-board PLL loop filter Easy access to digital input/output and diagnostic signals via input/output header (4 GPIOs) Status LEDs for diagnostic signals USB computer
radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO, and to generate
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