Transcription of EXPERIMENT 3: TTL AND CMOS CHARACTERISTICS - CLASSE
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EXPERIMENT 3: TTL AND CMOS CHARACTERISTICS - CLASSE
EXPERIMENT 3: TTL AND CMOS CHARACTERISTICS PURPOSE Logic gates are classified not only by their logical functions, but also by their logical families. In any implementation of a digital system, an understanding of a logic element's physical capabilities and limitations, determined by its logic family, are critical to proper operation. The purpose of this EXPERIMENT is to provide an understanding of some of the CHARACTERISTICS of the transistor-transistor logic (TTL) family and Complementary Metal Oxide Semiconductor logic (CMOS) family.
V as the input voltage is increased. Noise immunity is a measure of the ability of a digital circuit to avert logic level changes on signal lines when noise causes voltage level changes. (See Figure 3.3.) One measure of noise immunity is characterized by a pair of parameters: the dc HIGH and LOW noise margins, DC1 and DC0, respectively.
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