Transcription of FIFO Generator v12 - Xilinx
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FIFO Generator v12 - Xilinx
fifo Generator IP Product GuideVivado Design SuitePG057 June 24, 2015 fifo Generator June 24, 2015 Table of ContentsIP FactsChapter 1: OverviewNative Interface FIFOs .. 5 AXI Interface FIFOs.. 6 Feature Summary.. 8 Applications .. 60 Licensing and Ordering Information .. 63 Chapter 2: Product SpecificationPerformance .. 64 Resource Utilization .. 64 Port Descriptions .. 78 Chapter 3: Designing with the CoreGeneral Design Guidelines .. 93 Initializing the fifo Generator .. 95 fifo Usage and Control .. 95 Clocking.. 120 Resets .. 125 Actual fifo Depth .. 133 Latency .. 135 Special Design Considerations .. 148 Chapter 4: Design Flow StepsCustomizing and Generating the Native Core.
FIFO Generator v12.0 www.xilinx.com 5 PG057 June 24, 2015 Chapter 1 Overview The FIFO Generator core is a fully verified first-in first-out memory queue for use in any
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