Transcription of FIFO Generator v13 - Xilinx
{{id}} {{{paragraph}}}
Example: stock market
FIFO Generator v13 - Xilinx
fifo Generator IP Product GuideVivado Design SuitePG057 April 5, 2017 fifo Generator April 5, 2017 Table of ContentsIP FactsChapter 1: OverviewNative Interface FIFOs .. 5 AXI Interface FIFOs.. 6 Feature Summary.. 8 Applications .. 62 Licensing and Ordering Information .. 65 Chapter 2: Product SpecificationPerformance .. 66 Resource Utilization .. 77 Port Descriptions .. 77 Chapter 3: Designing with the CoreGeneral Design Guidelines .. 93 Initializing the fifo Generator .. 95 fifo Usage and Control .. 95 Clocking.. 121 Resets .. 126 Actual fifo Depth .. 134 Latency .. 136 Special Design Considerations .. 148 Chapter 4: Design Flow StepsCustomizing and Generating the Native Core .. 153 Customizing and Generating the AXI Core .. 170 Constraining the Core .. 182 Simulation .. 182 Synthesis and Implementation.
FIFO Generator v13.1 www.xilinx.com 4 PG057 April 5, 2017 Product Specification Introduction The Xilinx LogiCORE™ IP FI FO Generator core is a fully verified first-in first-out (FIFO) memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO configurations
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: