Transcription of Get Smart About Reset: Think Local, Not Global - …
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Get Smart About Reset: Think Local, Not Global - …
WP272 ( ) March 7, 1 2008 xilinx , Inc. All rights reserved. xilinx , the xilinx logo, and other designated brands included herein are trademarks of xilinx , Inc. All other trademarks are the property of their respective owners. One of the commandments of digital design states,"Thou shalt have a master reset for all flip-flops sothat the test engineer will love you, and yoursimulations will not remain undefined for timeeternal." So, some may be surprised to learn that applying aglobal reset to your FPGA designs is not a very goodidea and should be avoided. Clearly, this is acontroversial issue, so let's take a look at the reasonswhy such a design policy should be Paper: xilinx FPGAsWP272 ( ) March 7, 2008 Get Smart About Reset: Think local , Not GlobalBy: Ken ChapmanR2 ( ) March 7, 2008 Global Reset Isn't Timing-CriticalRGlobal Reset Isn't Timing-CriticalWhat a
Does It Really Matter? WP272 (v1.0.1) March 7, 2008 www.xilinx.com 3 R If the reset is released asynchronously to the clock (often the case), there is no way to
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