Transcription of Hardware and Layout Design Considerations for DDR …
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Hardware and Layout Design Considerations for DDR …
Freescale SemiconductorApplication Note Freescale Semiconductor, Inc., 2003, 2007. All rights reserved. Embedded systems that use double data rate memory (DDR) can realize increased performance over traditional single data rate (SDR) memories. As the name implies, DDR enables two data transactions to occur within a single clock cycle without doubling the applied clock or without to doubling the size of the data bus. This increased data bus performance is due to source-synchronous data strobes that permit data to be captured on both the falling and rising edges of the DDR can bring improved performance to an embedded Design , care must be observed in the schematic and Layout phases to ensure that desired performance is realized.
The AC logic levels are the points at the receiver where the AC input timing para meters (setup and hold) must be satisfied. The DC logic levels provide a point of hysteresis. When the input level crosses the DC reference point, the receiver switches to the new logic level and maintains this new state as long as the signal does not cross below the
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