Transcription of Hardware and Layout Design Considerations for DDR …
{{id}} {{{paragraph}}}
Example: air traffic controller
Hardware and Layout Design Considerations for DDR …
Freescale SemiconductorApplication Note Freescale Semiconductor, Inc., 2003, 2007. All rights reserved. Embedded systems that use double data rate memory (DDR) can realize increased performance over traditional single data rate (SDR) memories. As the name implies, DDR enables two data transactions to occur within a single clock cycle without doubling the applied clock or without to doubling the size of the data bus. This increased data bus performance is due to source-synchronous data strobes that permit data to be captured on both the falling and rising edges of the DDR can bring improved performance to an embedded Design , care must be observed in the schematic and Layout phases to ensure that desired performance is realized. Smaller setup and hold times, cleaner reference voltages, tighter trace matching, new I/O (SSTL-2) signaling, and the need for proper termination can present the board designer with a new set of challenges that were not present for SDR designs.
Besides memory, composite memory topologies can also include on-board logic analyzer connections and expansion DIMM cards with analyzer connections. The design guidelines in this document apply to Powe rQUICC™ products that leverage the DDR IP core and are based on a compilation of internal platforms designed by Freescale.
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: