Transcription of Hardware and Layout Design Considerations for DDR …
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Hardware and Layout Design Considerations for DDR …
Freescale SemiconductorApplication Note Freescale Semiconductor, Inc., 2003, 2007. All rights reserved. Embedded systems that use double data rate memory (DDR) can realize increased performance over traditional single data rate (SDR) memories. As the name implies, DDR enables two data transactions to occur within a single clock cycle without doubling the applied clock or without to doubling the size of the data bus. This increased data bus performance is due to source-synchronous data strobes that permit data to be captured on both the falling and rising edges of the DDR can bring improved performance to an embedded Design , care must be observed in the schematic and Layout phases to ensure that desired performance is realized. Smaller setup and hold times, cleaner reference voltages, tighter trace matching, new I/O (SSTL-2) signaling, and the need for proper termination can present the board designer with a new set of challenges that were not present for SDR designs.
Hardware and Layout Design Considerations for DDR Memory Interfaces, Rev. 6 2 Freescale Semiconductor SSTL-2 and Termination Design challenges confronting the board designer can be summarized as follows: • Routing requirements † Power supply and decoupling, which includes the DDR devices and controller, the termination rail generation (V
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