Hi3531A H.264 CODEC Processor Brief Data Sheet

Hi3531A . Hi3531A CODEC Processor Brief data Sheet Key Specifications interface Two 8-bit interfaces that can form a 16-bit interface Processor Core 108 MHz/144 MHz 4xD1/960H TDM inputs for each 8- z Dual-core ARM Cortex GHz bit interface (32xD1/32x960H real-time video inputs in 32 KB L1 I-cache, 32 KB L1 D-cache total). 256 KB L2 cache 144 MHz 2x720p TDM inputs for each 8-bit NEON and FPU interface (16x720p@30 fps real-time video inputs in Video Encoding/Decoding Protocols total). 4x720p TDM inputs through MHz dual-edge z baseline/main/high profile sampling or 297 MHz single-edge sampling for each 8- z MJPEG/JPEG baseline bit interface (32x720p@30 fps real-time video inputs in Video Encoding/Decoding total). z multi-stream encoding and decoding MHz inputs in Y/C interleaved mode for 8x1080p@30 fps encoding+8xCIF@30 fps each 8-bit interface (8x1080p@30 fps real-time video encoding+4x1080p@30 fps inputs in total).

Hi3531A Hi3531A H.264 CODEC Processor Brief Data Sheet Issue 03 (2016-02-29) HiSilicon Proprietary and Confidential Copyright © HiSilicon Technologies Co., Ltd

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