Transcription of High Performance, 3.2 GHz, 14-Output Fanout Buffer Data ...
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High Performance, 3.2 GHz, 14-Output Fanout Buffer Data ...
High Performance, GHz, 14-Output Fanout BufferData Sheet HMC7043 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, Box 9106, Norwood, MA 02062-9106, : 2015 2016 Analog Devices, Inc. All rights reserved. Technical Support FEATURES JEDEC JESD204B support Low additive jitter: <15 fs rms at MHz (12 kHz to 20 MHz) Very low noise floor: dBc/Hz at MHz Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200 MHz JESD204B-compatible system reference (SYSREF) pulses 25 ps analog and clock input cycle digital delay independently programmable on each of 14 clock output channels SPI- programmable adjustable noise floor vs.
local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end ASICs. The HMC7043 can generate up to seven DCLK and SYSREF clock pairs per the JESD204B interface requirements. The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths
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