Transcription of High- performance EPLD
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Example: tourism industry
High- performance EPLD
1 TQFPTop View12345678910113332313029282726252423I /OI/OI/OGNDI/OI/OI/OI/OVCCI/OI/OI/OI/OI/ OI/OVCCI/OI/OI/OI/OGNDI/O444342414039383 73635341213141516171819202122I/OI/OI/OI/ OGNDVCCI/OI/OI/OI/OI/OI/OI/OI/O/PDVCCOE2 /IGCLR/IOE1/ICLK/IGNDI/OI/OPLCCTop View789101112131415161739383736353433323 13029I/OI/OI/OGNDI/OI/OI/OI/OVCCI/OI/OI/ OI/OI/OI/OVCCI/OI/OI/OI/OGNDI/O654321444 34241401819202122232425262728I/OI/OI/OI/ OGNDVCCI/OI/OI/OI/OI/OI/OI/OI/O/PDVCCOE2 /IGCLR/IOE1/ICLK/IGNDI/OI/OPin ConfigurationsPinNameFunctionCLKC lockILogic InputsI/OBi-directional BuffersGCLRR egister Reset (active low)OE1, OE2 Output Enable (active low)VCC+5V SupplyPDPower-down (active high)Features High- density, High- performance Electrically-erasable Complex Programmable logic Device 44-pin, 32 I/O CPLD ns Maximum Pin-to-pin Delay Registered Operation Up to 125 MHz Fully Connected Input and Feedback logic Array Backward Compatibility with ATF1500/L Software and Hardware Flexible logic Macrocell D/T/Latch Configurable Flip-flops Global and Individual
ATF1500A(L) 3 Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals within a regional bus are connected to …
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