High-speed, high-bandwidth DRAM memory bus with …

1 HOT INTERCONNECT 2001 Systems Development , high-bandwidth DRAM memory bus withCrosstalk transfer logic (XTL) interfaceHideki OsakaHitachi Ltd., Kanagawa, KomatsuHitachi Ltd., Kanagawa, HatanoElpida memory Inc., Kanagawa, WadaHitachi Ltd., Tokyo, ELPIDA MEMORYHOT INTERCONNECT 2001 Systems Development Requirements of server memory system Background of high-speed interconnect Mechanism of XTL Design of evaluation system m process TEST chip ( hysteresis receiver) 8 modules mountable PCB w/ folding coupler XTL Experimental result Conclusion2 HOT INTERCONNECT 2001 Systems Development of server memory system memory system for high-performance workstation and server High band width Large capacity Low latency access Low power High availability Cost02004006008001000120019 97 19 98 19 99 2000 20012002 Freq [MHz]YearDDR-XTLCPUDRAMT argetHOT INTERCONNECT 2001 Systems Development Bus cheaper than point-to-point Low pin count and small real estate owing to sharing signal However, hard to manage trade-off speed-up and noise ISI (Inter Symbol Interference)

1 HOT INTERCONNECT 2001 Systems Development Laboratory 1 2001.08 High-speed, high-bandwidth DRAM memory bus with Crosstalk Transfer Logic (XTL) interface

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  Memory, With, Transfer, Interface, Logic, Crosstalk, Memory bus with crosstalk transfer logic

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