Transcription of High Speed Layout Design Guidelines
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High Speed Layout Design Guidelines
Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Freescale SemiconductorApplication NoteDocument Number: AN2536 Rev. 2, 04/20061 AbstractDesign of memory systems becomes more complex as the operation frequency increases in a low-power environment. A number of criteria should be considered to achieve maximum system performance under these conditions. The external memory bus is intended to work with PC100 grade memory. Care must be taken in board Layout to achieve a system capable of maximum bus rates at low document describes the recent investigation into the maximum memory bus frequency of a low-power memory system in terms of stability, capacitive loading, and production margin. This data will be useful to customers in their Design of low power high Speed memory systems with the applications processorsThis document applies to the following devices, collectively called throughout: MC9328MX1 MC9328 MXL MC9328 MXS High Speed Layout Design GuidelinesMC9328MX1, MC9328 MXL, and MC9328 MXSC ontents1 Abstract.
above GND is much slower in a stripline layout comp ared with a microstrip la yout. A stripline layout has ... Microstrip Layout Propagation Delay Eqn. 7 Stripline Layout Propagation Delay Eqn. 8 Figure 8. Propagation Delay vs. Dielectric Constant For Microstrip and Stripline Traces ... traces closer than three times the dielectric height.
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