Transcription of I2C bus specifications - CERN
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I2C bus specifications - CERN
i2c bus specifications for the CMS tracker 2S & PS modules V 21/4/2016 2 Revision History Version Date Comments 22/11/2015 First draft 21/4/2016 Device ID extended to 3 bytes. Table 2 revised to reflect the non-programmable CiC address field. Added electrical and timing specifications . 3 1 INTRODUCTION The present document discusses the implementation of the I2C serial communication bus in the CMS Outer Tracker PS (Pixel-Stip) & 2S (Strip-Strip) modules. The use of the I2C bus is to monitor and control the operation of the front-end ASICs populating the PS & 2S modules. The aim of the document is to present guidelines for the development of I2C circuitry of the front-end ASICs. It should be noted that only a subset of features of the I2C Bus standard are necessary to support the functionality of the ASICs of the PS & 2S modules and therefore the design guidelines are limited to these features.
The I2C Bus Topology for the PS and 2S is shown in Figure 1. The optical link communication ASIC; namely the lpGBT (low power GigaBit Transceiver) is equipped with two independent I2C master interfaces that realize two independent I2C busses. The lpGBT I2C master interface is the only master interface permitted to connect on the bus.
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