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IJESRT
[Praveena, 3(1): January, 2014] ISSN: 2277-9655 Impact Factor: http: // (C)International Journal of Engineering Sciences & Research Technology [485-490] IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY A Novel Approach to FPGA Realization of FIR Filters by Systolization Using Distributed Arithmetic Assistant Professor, Department of ECE, PSNA College Of Engineering & Technology ,Dindigul, India Abstract Distributed arithmetic (DA) is bit serial in nature and is basically re-arrangement of multiply and accumulate operation. In this project we present the design techniques of 1D and 2D fully pipelined computing structures for area, delay, power efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA) based inner-product computation.
http: // www.ijesrt.com (C) International Journal of Engineering Sciences & Research Technology
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