Integrated 3-Port 10/100 Managed Switch with PHYs

2017 Microchip Technology Inc. DS00002348A-page 1 Features Advanced Switch Features- IEEE VLAN Support for Up to 16 Groups (Full Range of VLAN IDs)- VLAN ID Tag/Untag Options, Per Port Basis- IEEE Tag Insertion or Removal on a Per Port Basis (Egress)- Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis- Broadcast Storm Protection with Percent Con-trol (Global and Per Port Basis)- IEEE Rapid Spanning Tree Protocol Support- Tail Tag Mode (1 byte Added before FCS) Sup-port at Port 3 to Inform the Processor which Ingress Port Receives the Packet and its Prior-ity- Bypass Feature that Automatically Sustains the Switch Function between Port 1 and Port 2 when CPU (Port 3 Interface) Goes into Sleep Mode- Self-Address Filtering- Individual MAC Address for Port 1 and Port 2- Supports RMII Interface and 50 MHz Reference Clock Output- MAC MII Interface Supports Both MAC and PHY Modes- IGMP Snooping (IPv4) Support for Multicast Packet Filtering- IPv4/IPv6 QoS Support- MAC Filtering Function to Forward Unknown Unicast Packets to Specified Port Comprehensive Configuration R

KSZ8873MLL/FLL/RLL DS00002348A-page 6 2017 Microchip Technology Inc. TABLE 2-1: SIGNALS Pin Number Pin Name Type Note 2-1 Description 1 RXM1 I/O Physical receive or transmit signal (– differential)

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  With, Switch, Differential, Managed, Phys, 10 100 managed switch with phys

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