Transcription of JESD204 PHY v4 - Xilinx
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JESD204 PHY v4 - Xilinx
JESD204 PHY IP Product GuideVivado Design SuitePG198 ( ) April 8, 2021 JESD204 PHY ( ) April 8, of ContentsIP FactsChapter 1: OverviewApplications .. 7 Licensing and Ordering Information .. 9 Chapter 2: Product SpecificationPerformance and Resource Utilization .. 10 Port Descriptions .. 10 AXI4-Lite Register Space .. 24 Line Rate Switching .. 41 Chapter 3: Designing with the CoreJESD204 PHY Configuration Options.. 54 General Design Guidelines .. 55 Clocking.. 56 Resets .. 57 Protocol Description .. 58 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 59 Constraining the Core .. 64 Simulation .. 65 Synthesis and Implementation .. 65 Chapter 5: Example DesignChapter 6: Test BenchAXI Interface.. 73 Appendix A: Verification, Compliance, and InteroperabilitySimulation .. 74 Hardware Testing .. 74 Send FeedbackJESD204 PHY ( ) April 8, B: DebuggingFinding Help on.
JESD204 PHY v4.0 5 PG198 (v4.0) April 8, 2021 www.xilinx.com Chapter 1 Overview The LogiCORE™ IP JESD204 PHY core implements: • A JESD204B Physical interface supporting line rates between 1.0 and 12.5 Gb/s on 1 to 12
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