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Leakage Current Reduction in CMOS VLSI Circuits by Input ...

1 Leakage Current Reduction in cmos vlsi Circuits by Input vector control Afshin Abdollahi University of Southern California Los Angeles CA 90089 Farzan Fallah Fujitsu Laboratories of America San Jose CA 94085 Massoud Pedram University of Southern California Los Angeles CA 90089 Abstract The first part of this paper describes two runtime mechanisms for reducing the Leakage Current of a cmos circuit . In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total Leakage Current in the circuit . This minimization is possible because the Leakage Current of a cmos gate is strongly dependent on the Input combination applied to its inputs.

1 Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control Afshin Abdollahi University of Southern California Los Angeles CA 90089

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