Transcription of Lecture 12: MOS Transistor Models
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Lecture 12: MOS Transistor Models
Department of EECSU niversity of California, BerkeleyEECS 105 Fall 2003, Lecture 12 Lecture 12: MOS Transistor ModelsProf. NiknejadDepartment of EECSU niversity of California, BerkeleyEECS 105 Fall 2003, Lecture 12 Prof. A. NiknejadLecture Outline MOS Transistors ( ) I-V curve (Square-Law Model) Small Signal Model (Linear Model)Department of EECSU niversity of California, BerkeleyEECS 105 Fall 2003, Lecture 12 Prof. A. NiknejadObserved Behavior: ID-VGS Current zero for negative gate voltage Current in Transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearlyGSVDSITVGSVDSIDSVD
Drain mobile charge goes to zero (region is depleted), the remaining elecric ... Gate Bias. Department of EECS University of California, Berkeley EECS 105Fall 2003, Lecture 12 Prof. A. Niknejad Output Resistance ro Defined as the inverse of the change in drain current due
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