Lecture 2 – Combinational Circuits and Verilog

Lecture 2 Combinational Circuits and Verilog CSE P567 Example: r1 = r2 + r3 We need: Registers Adder function ( Combinational logic) Wires Example: r1 = r2 + r3 We need: Registers adder function ( Combinational logic) Wires Selection function We won t always want r2 and r3 Combinational Logic functions with no state Output is a function of the inputs only no history add subtract multiply count-ones FSM next state function All computation is done in binary Primitive circuit values are on/off, Vdd/GND, current/no current Review: Binary Encoding of Numbers Unsigned numbers bn-12n-1 + bn-22n-2 + .. + b020 2s complement encoding of signed numbers -bn-12n-1 + bn-22n-2 + .. + b020 Same adder works for both unsigned and signed numbers To negate a number, invert all bits and add 1 As slow as add in worst case Binary Addition Simple addition algorithm works: 0 1 1 0 +6 1 1 0 1 -3 --------- Binary Addition Simple addition algorithm works: Note: we drop the carry out of the high-order bit Each bit computes the same simple functions Sum = f(a, b, Cin) Cout = f(a, b, Cin) Ripple carry adder 1 1 0 0 0 1 1 0 +6 1 1 0 1 -3 --------- 0 0 1 1 3 Ripple-Carry Adder Each bit computes the same simple functions Sum = f(a, b, Cin) Cout = f(a, b, Cin) If we can write the function as a Boolean equation, we can generate the circuit Combinational Logic Design We can translate a Boolean func

Multi-Level Logic Minimization Factor function into smaller functions Smaller gates Fewer gates Deeper circuit – cost/performance tradeoff Needed for FPGAs and semi-custom ASICs Circuit libraries with “small” gates Developed in the 1980s and 90s Much more difficult problem than 2-level minimization

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  Functions, Minimization

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