Transcription of Low Power VLSI Design using Clock-Gating Technique
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Low Power VLSI Design using Clock-Gating Technique
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 4 Issue 7, July 2015 3270 ISSN: 2278 1323 All Rights Reserved 2015 IJARCET Abstract In this paper clock gating Technique is presented for low Power vlsi (very large scale integration) circuit Design . With the scaling of technology and the need for higher performance and more functionality, Power dissipation is becoming a major bottleneck for microprocessor designs. Because clock Power can be significant in high-performance processors, we propose a deterministic Clock-Gating (DCG) Technique which effectively reduces clock Power . In this paper a 4-bit synchronous counter, Arithmetic and Logic unit(ALU) ,scrambler and descrambler is designed using clock gating.
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 4 Issue 7, July 2015 3271 (a) (b) Figure 1. Schematic of Latch Element
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