Transcription of MX25L4005, MX25L8005 - mct.net
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MX25L4005, MX25L8005 - mct.net
REV. , MAY. 31, 20051P/N: PM1130MX25L4005, MX25L80054M/8M-BIT [x 1] CMOS SERIAL FLASHPRELIMINARYFEATURESGENERAL Serial Peripheral Interface (SPI) compatible -- Mode 0and Mode 3 4,194,304 x 1 bit structure for 4M; 8,388,608 x 1 bitstructure for 8M 128 Equal Sectors with 4K byte each ( mx25l4005 )256 Equal Sectors with 4K byte each ( MX25L8005 )- Any Sector can be erased individually 8 Equal Blocks with 64K byte each ( mx25l4005 )16 Equal Blocks with 64K byte each ( MX25L8005 )- Any Block can be erased individually Single Power Supply Operation- to volt for read, erase, and program operations Latch-up protected to 100mA from -1V to Vcc +1V Low Vcc write inhibit is from to High Performance- Fast access time: 70 MHz serial clock (15pF + 1 TTLLoad) and 66 MHz serial clock (30pF + 1 TTL Load)- Fast program time: (typ.)
3 P/N: PM1130 REV. 0.04, MAY. 31, 2005 MX25L4005, MX25L8005 BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y-Decoder X-Decoder Data Register SRAM
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