Transcription of Optimal SelectIO Interface VREF Generation Circuits - Xilinx
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Optimal SelectIO Interface VREF Generation Circuits - Xilinx
XAPP1087 ( ) April 24, 1 Copyright 2013 Xilinx , Inc. Xilinx , the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective variety of PCB SelectIO Interface VREF Generation Circuits are used in FPGA design. Sometimes, large amounts of noise (200 400 mV) can be found on VREF pins even with a PCB VREF Generation circuit that has been successful in previous designs. The presence of large amounts of VREF noise can lead to loss of design margin with high performance SelectIO interfaces, such as wide DDR3 memory interfaces. This application note examines the source of this VREF noise and recommends optimized PCB SelectIO VREF Generation InputFigure 1 shows a simplified view of a VREF circuit inside the FPGA.
Conclusion XAPP1087 (v1.0) April 24, 2013 www.xilinx.com 6 Conclusion As FPGA SelectIO pins increase in frequency, noise on VREF pins occurs more frequently. An optimized VREF generation circuit similar to the circuit presented in this application note provides protection from the issue of VREF noise as SelectIO switching rates continue to improve. ...
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