Optimizing FPGA-based Accelerator Design for Deep ...

Optimizing FPGA-based Accelerator Design for DeepConvolutional Neural NetworksChen Cong2,3,1, for Energy-Efficient Computing and Applications, Peking University, China2 Computer Science Department, University of California, Los Angeles, USA3 PKU/UCLA Joint Research Institute in Science and EngineeringABSTRACTC onvolutional neural network (CNN) has been widely em-ployed for image recognition because it can achieve high ac-curacy by emulating behavior of optic nerves in living crea-tures. Recently, rapid growth of modern applications basedon deep learning algorithms has further improved researchand implementations. Especially, various accelerators fordeep CNN have been proposed based on FPGA platformbecause it has advantages of high performance, reconfigura-bility, and fast development round, etc.

Permission to make digital or hard copies of all or part of this work for personal or ... based accelerators have attracted more and more attention of researchers because they have advantages of good perfor-mance, high energy e ciency, fast development round, and ... each sized 48 feature maps. Layer1’s kernel size is 11x11 and the sliding window

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