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Optimizing FPGA-based Accelerator Design for Deep ...

Optimizing FPGA-based Accelerator Design for DeepConvolutional Neural NetworksChen Cong2,3,1, for Energy-Efficient Computing and Applications, Peking University, China2 Computer Science Department, University of California, Los Angeles, USA3 PKU/UCLA Joint Research Institute in Science and EngineeringABSTRACTC onvolutional neural network (CNN) has been widely em-ployed for image recognition because it can achieve high ac-curacy by emulating behavior of optic nerves in living crea-tures. Recently, rapid growth of modern applications basedon deep learning algorithms has further improved researchand implementations. Especially, various accelerators fordeep CNN have been proposed based on FPGA platformbecause it has advantages of high performance, reconfigura-bility, and fast development round, etc. Although currentFPGA accelerators have demonstrated better performanceover generic processors, the Accelerator Design space has notbeen well exploited.

FPGA; Roo ine Model; Convolutional Neural Network; Ac-celeration 1. INTRODUCTION Convolutional neural network (CNN), a well-known deep learning architecture extended from arti cial neural network, has been extensively adopted in various applications, which include video surveillance, mobile robot vision, image search

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