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Optimizing FPGA-based Accelerator Design for Deep ...

Optimizing FPGA-based Accelerator Design for DeepConvolutional Neural NetworksChen Cong2,3,1, for Energy-Efficient Computing and Applications, Peking University, China2 Computer Science Department, University of California, Los Angeles, USA3 PKU/UCLA Joint Research Institute in Science and EngineeringABSTRACTC onvolutional neural network (CNN) has been widely em-ployed for image recognition because it can achieve high ac-curacy by emulating behavior of optic nerves in living crea-tures. Recently, rapid growth of modern applications basedon deep learning algorithms has further improved researchand implementations. Especially, various accelerators fordeep CNN have been proposed based on FPGA platformbecause it has advantages of high performance, reconfigura-bility, and fast development round, etc.

based on traditional arti cial neural networks. The purpose of this classi er is to decide the likelihood of categories that the input (e.g. image) might belong to. ... will form the set of input feature maps for the next convo-lutional layer. The pseudo code of a convolutional layer can be written as that in Code 1. Figure 1: Graph of a ...

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