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Ph.D. Progress Report --- Report #2 - Ryerson University

Progress Report --- Report #2(March 2001 -- March 2002)by Andy Gean YeThis Report summarizes my research Progress from March 2001 to March 2002. This timeperiod corresponds to part of the third and fourth year of my candidacy. As stated in my firstreport, the goal of my research is to create an efficient FPGA architecture for datapath cir-cuits. My research methodology is empirical and consists of three phases, two of which have beencompleted as of March 2002. The first phase consisted of gathering a suite of real benchmark cir-cuits.

Ph.D. Progress Report --- Report #2 (March 2001 -- March 2002) by Andy Gean Ye This report summarizes my Ph.D. research progress from March 2001 to March 2002. This time period corresponds to part of the third and fourth year of my Ph.D. candidacy. As stated in my first

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