Transcription of Phase-Locked Loop Design Fundamentals - NXP
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Phase-Locked Loop Design Fundamentals - NXP
Freescale Semiconductor, Inc., 1994, 2006. All rights SemiconductorApplication NoteDocument Number: AN535 Rev. , 02/2006 AbstractThe fundamental Design concepts for Phase-Locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the basic loop performance are given in conjunction with a brief Design document contains references to obsolete part numbers and is offered for technical information purpose of this application note is to provide the electronic system designer with the necessary tools to Design and evaluate Phase-Locked Loops (PLL) configured with integrated circuits. The majority of all PLL Design problems can be approached using the Laplace Transform technique.
The phase detector, filter, and VCO/VCM compose the feed forward path with the feedback path containing the programmable divider. Removal of the programmable counter produces unity gain in the feedback path (N = 1). As a result, the output frequency is then equa l to that of the input.
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