Transcription of PIC32 Family Reference Manual - Section 2. CPU …
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PIC32 Family Reference Manual - Section 2. CPU …
2007-2012 Microchip Technology 2-1 CPU for Devices with M4K Core2 Section 2. CPU for Devices with M4K CoreHIGHLIGHTSThis Section of the Manual contains the following .. Overview .. CPU Details .. Considerations When Writing to CP0 Registers .. Release 2 Details .. CPU bus .. System Busses .. Status and Exception Mechanism .. Model .. 0 (CP0) Execution .. Model .. Instructions, Grouped By Initialization .. of a Reset .. Application Notes .. 2-62 PIC32 Family Reference ManualDS61113E-page 2-2 2007-2012 Microchip Technology INTRODUCTION The PIC32 MCU is a complex system-on-chip (SoC) that is based on the M4K Microprocessorcore from MIPS Technologies. The M4K is a state-of-the-art, 32-bit, low-power, RISC proces-sor core with the enhanced MIPS32 Release 2 Instruction Set Architecture (ISA).This chapter provides an overview of the CPU features and system architecture of the PIC32family of microcontrollers that are based on the M4K processor Features Up to DMIPS/MHz of performance Programmable prefetch cache memory to enhance execution from Flash memory (not available on all devices; refer to the specific device data sheet to determine availability) 16-bit Instruction mode (MIPS16e ) for compact code Vectored interrupt controller with up to 96 interrupt sources Programmable User and Kernel modes of operation Atomic bit manipulations on peripheral regis
© 2007-2012 Microchip Technology Inc. DS61113E-page 2-7 Section 2. CPU for Devices with M4K® Core CPU for Devices with M4K ® Core 2 2.3.1.5 W STAGE – WRITEBACK
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