Transcription of Predicting the Phase Noise and Jitter ... - Designer’s Guide
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Predicting the Phase Noise and Jitter ... - Designer’s Guide
The Designer s Guide Communitydownloaded from 2002 2019, Kenneth S. Kundert All Rights Reserved1 of 52 Version 4i, 23 October 2015 Two methodologies are presented for Predicting the Phase Noise and Jitter of a PLL-based frequency synthesizer using simulation that are both accurate and efficient. The methodologies begin by characterizing the Noise behavior of the blocks that make up the PLL using transistor-level RF simulation. For each block, the Phase Noise or Jitter is extracted and applied to a model for the entire TermsPhase-locked loop, PLL simulation, PLL Phase -domain modeling, frequency synthe-sizer, oscillator Phase Noise , Jitter , cyclostationary Noise , charge-pump Noise , Phase -detector Noise , frequency divider Noise , SpectreRF, paper was written in August 2002.
4 of 52 The Designer’s Guide Community www.designers-guide.org also rules out any PLL that is implemented wi th a phase detector that has a dead zone. A dead zone has the effect of opening the loop and letting the phase drift seemingly at ran-dom when the phase of the reference and the output of the voltage-controlled oscillator (VCO) are close.
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