Transcription of Predicting the Phase Noise and Jitter of PLL-Based ...
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Predicting the Phase Noise and Jitter of PLL-Based ...
The Designer s Guide Communitydownloaded from 2002 2019, Kenneth S. Kundert All Rights Reserved1 of 52 Version 4i, 23 October 2015 Two methodologies are presented for Predicting the Phase Noise and Jitter of a PLL-Based frequency synthesizer using simulation that are both accurate and efficient. The methodologies begin by characterizing the Noise behavior of the blocks that make up the PLL using transistor-level RF simulation. For each block, the Phase Noise or Jitter is extracted and applied to a model for the entire TermsPhase-locked loop, PLL simulation, PLL Phase -domain modeling, frequency synthe-sizer, oscillator Phase Noise , Jitter , cyclostationary Noise , charge-pump Noise , Phase -detector Noise , frequency divider Noise , SpectreRF, paper was written in August 2002. It was last updated on March 10, 2019.
components at frequencies that are multiples of the referen ce frequency. Do so by strob-ing at the reference frequency. In this case, if the strobed VCO control voltage varies in any significant way the PLL does not have a periodic solution. If the PLL has a periodic solution, then in concept it is always possible to apply Spec-
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