Transcription of R XC2C64A CoolRunner-II CPLD - Xilinx
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R XC2C64A CoolRunner-II CPLD - Xilinx
0. R. XC2C64A CoolRunner-II CPLD. DS311 ( ) November 19, 2008 0 0 Product Specification Features Description Optimized for systems The CoolRunner-II 64-macrocell device is designed for both - As fast as ns pin-to-pin logic delays high performance and low power applications. This lends - As low as 15 A quiescent current power savings to high-end communication equipment and Industry's best micron CMOS CPLD high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reli- - Optimized architecture for effective logic synthesis ability is improved. - Multi- voltage I/O operation to Available in multiple package options This device consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
VCC Supply voltage for internal logic and input buffers Commercial TA = 0°C to +70°C 1.7 1.9 V Industrial TA = –40°C to +85°C 1.7 1.9 V VCCIO Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V
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