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RISC-V ASSEMBLY LANGUAGE Programmer Manual Part I

RISC-V ASSEMBLYLANGUAGEP rogrammer ManualPart Ideveloped by: SHAKTI Development Team @ iitm @ Proprietary NoticeCopyrightc 2020,Shakti @ IIT rights reserved. Information in this document is provided as is , with all @ IIT Madrasexpressly disclaims all warranties, representations, and conditions ofany kind, whether express or implied, including, but not limited to, the implied warranties orconditions of merchant ability, fitness for a particular purpose and @ IIT Madrasdoes not assume any liability rising out of the application or use of anyproduct or circuit, and specifically disclaims any and all liability, including without limitationindirect, incidental, special, exemplary, or consequential @ IIT Madrasreserves the right to make changes without further notice to any Release 12, 2020 Initial 07, 2020 Updates and adding new 14, 2021 Update MUL descriptions for unsignedTable of Notice.

RISC-V pronounced as “RISC-five”, is an open-source standard Instruction Set Architecture (ISA), designed based on Reduced Instruction Set Computer (RISC) principles. With a flexible architecture to build systems ranging from a simple microprocessor to complex multi-core systems, RISC-V caters to any market.

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