Transcription of RTL-to-Gates Synthesis using Synopsys Design Compiler
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RTL-to-Gates Synthesis using Synopsys Design Compiler
RTL-to-Gates Synthesis using Synopsys Design CompilerCS250 Tutorial 5 (Version 091210b)September 12, 2010 Yunsup LeeIn this tutorial you will gain experience using Synopsys Design Compiler (DC) to perform hardwaresynthesis. A Synthesis tool takes an RTL hardware description and a standard cell library as inputand produces a gate-level netlist as output. The resulting gate-level netlist is a completely structuraldescription with standard cells only at the leaves of the Design . Internally, a Synthesis tool performsmany steps including high-level RTL optimizations, RTL to unoptimized boolean logic, technologyindependent optimizations, and finally technology mapping to the available standard cells. GoodRTL designers will familiarize themselves with the target standard cell library so that they candevelop an intuition on how their RTL will be synthesized into gates. In this tutorial you will useSynopsys Design Compiler to elaborate RTL, set optimization constraints, synthesize to gates, andprepare various area and timing reports.
Sep 12, 2010 · September 12, 2010 Yunsup Lee In this tutorial you will gain experience using Synopsys Design Compiler (DC) to perform hardware synthesis. A synthesis tool takes an RTL hardware description and a standard cell library as input and produces a gate-level netlist as output. The resulting gate-level netlist is a completely structural
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