Sample & Hold Circuits - Pennsylvania State University

CSE 577 Spring2011 Sample & hold CircuitsSample & hold CircuitsCSE 577 Spring 2011 Sample & hold Circuits Sample & hold Circuits Insoo Kim, Kyusun ChoiMixed Signal CHIP Design of Computer Science & EngineeringDepartment of Computer Science & EngineeringThe Pennsylvania State UniversityBasic Sample and hold circuit ConfigurationBasic Sample and hold circuit Configuration Concept MOSFET S&H CircuitInsoo Kim3/14/2011 Design Issues of cmos S&HDesign Issues of cmos S&H Sampling Moment Distortion Finite Clock rising/falling time results in distortionriseclockstVat2= Clock Feed-through Overlap cap. of MOS Switch creates an sampling error during clock transition time MOS Switch Charge Injection Some charge in the MOS channel flow to Source and Drain, then result in an error. holdThGSoxQVVVCQ = = ),(Insoo Kim3/14/2011 HholdThGSoxCQ),(Solutions for Reducing Sampling DistortionSolutions for Reducing Sampling Distortion Differential S&H circuit Sample Clock Bootstrapping Sampling distortion can be reduced by increasing clock amplitudeInsoo Kim3/14/2011 Sample Clock Bootstrap Circuits (I) Sample Clock Bootstrap Circuits (I) Basic clock bootstrap circuitBooted ClockClockSimulation ResultInsoo Kim3/14/2011 Sample Clock Bootstrap Circuits (II) Sample Clock Bootstrap Circuits (II) Differential sampling clock bootstrap circuitDifferential Sampling Booted Cl

Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters- 2nd Edition,” Kluwer Academic Publishers, 2003.Kluwer Academic Publishers, 2003. B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995. 3/14/2011 Insoo Kim

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