Transcription of Self-biased high-bandwidth low-jitter 1-to-4096 multiplier ...
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Self-biased high-bandwidth low-jitter 1-to-4096 multiplier ...
IEEE JOURNAL OF solid -STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003 1795. Self-biased high-bandwidth low-jitter 1-to-4096 . multiplier Clock Generator PLL. John G. Maneatis, Member, IEEE, Jaeha Kim, Student Member, IEEE, Iain McClatchie, Jay Maxey, and Manjusha Shankaradas Abstract A Self-biased phase-locked loop (PLL) uses a sampled specific circuit parameters, such as the charge pump current feedforward filter network and a multistage inverse-linear pro- and the loop filter resistance. Thus, these parameters must vary grammable current mirror for constant loop dynamics that scale with output frequency and multiplication factor.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003 1795 Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL
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