Transcription of Sequential 4-bit Adder Design Report - ianhung
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Sequential 4-bit Adder Design Report - ianhung
UNIVERSITY OF WATERLOO. Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (iXXXXXX), 99 XXXXXX. Annette Lo (aXXXXXX), 99 XXXXXX. Pamela Torres (pXXXXXX), 99 XXXXXX. August 8, 2003. Table of Contents List of Figures .. iii List of Tables .. iv 1. Project Requirements .. 1. Functionality of Binary Adder .. 1. Design 2. Adder Architecture 2. Flip-flop Architecture Selection .. 6. Optimization Techniques .. 6. Sizing .. 6. Pre-layout Simulation 8. Layout of Sequential Four-Bit Adder .. 9. Post-layout Simulation Results.
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (iXXXXXX), 99XXXXXX
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