Transcription of Set-Associative Cache Architecture
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Set-Associative Cache Architecture
chapter 5 Set Associative Caches1 COMPUTERORGANIZATIONANDDESIGNThe Hardware/Software Interface5thEditionChapter 5 Set-Associative Cache ArchitecturePerformance SummarynWhen CPU performance increases:nMiss penalty becomes more proportion of time spent on memory clock rate:nMemory stalls account for more CPU t neglect Cache behavior when evaluating system 5 Set Associative Caches2 Review: Reducing Cache Miss Rates #1 Allow more flexible block placementnIn a direct mapped Cache a memory block maps to exactly one Cache the other extreme, we could allow a memory block to be mapped to anycache block fully associative compromise is to divide the Cache into sets,each of which consists of n ways (n-way set associative).
Chapter 5 —Set Associative Caches 10 Cortex-A8 Data Cache Miss Rates FIGURE 5.45 Data cache miss rates for ARM Cortex-A8 when running Minnespec, a small version of SPEC2000.Applications with larger memory footprints tend to have higher miss rates in both L1 and L2. Note that the L2 rate is the global miss rate; that is, counting all references,
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