Transcription of SHARC+ Dual-Core DSP with Arm Cortex-A5
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SHARC+ Dual-Core DSP with Arm Cortex-A5
SHARC+ Dual-Core DSP with Arm Cortex-A5 . ADSP-SC582/SC583/SC584/SC587/SC589/ADSP- 21583/21584/21587. SYSTEM FEATURES 19 mm 19 mm 349/529 BGA ( pitch), RoHS compliant Dual enhanced SHARC+ high performance floating-point Low system power across automotive temperature range cores memory . Up to 500 MHz per SHARC+ core Large on-chip L2 SRAM with ECC protection, up to 256 kB. Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core On-chip L2 ROM (512 kB). with parity (optional ability to configure as cache). Two Level 3 (L3) interfaces optimized for low system power, 32-bit, 40-bit, and 64-bit floating-point support providing a 16-bit interface to DDR3 (supporting V. 32-bit fixed point capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices Byte, short-word, word, long-word addressed ADDITIONAL FEATURES. Arm Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle Security and Protection 32 kB L1 instruction cache/32 kB L1 data cache Cryptographic hardware accelerators 256 kB Level 2 (L2) cache with parity Fast secure boot with IP protection Powerful DMA system Support for Arm TrustZone On-chip memory protection Accelerators Integrated safety features High performance pipelined FFT/IFFT engine FIR, IIR, HAE, SINC offload engines AEC-Q100 qualified for automotive applications SYSTEM CONTROL PERIPHERALS.
applications with large, on-chip, static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhance-ments and branch prediction, while maintaining instruction set compatibility to previous SHARC products.
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