Transcription of SHARC+ Dual-Core DSP with Arm Cortex-A5 - Analog Devices
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SHARC+ Dual-Core DSP with Arm Cortex-A5 - Analog Devices
SHARC+ Dual-Core DSP with Arm Cortex-A5 . ADSP-SC582/SC583/SC584/SC587/SC589/ADSP- 21583/21584/21587. SYSTEM FEATURES 19 mm 19 mm 349/529 BGA ( pitch), RoHS compliant Dual enhanced SHARC+ high performance floating-point Low system power across automotive temperature range cores MEMORY. Up to 500 MHz per SHARC+ core Large on-chip L2 SRAM with ECC protection, up to 256 kB. Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core On-chip L2 ROM (512 kB). with parity (optional ability to configure as cache). Two Level 3 (L3) interfaces optimized for low system power, 32-bit, 40-bit, and 64-bit floating-point support providing a 16-bit interface to DDR3 (supporting V. 32-bit fixed point capable DDR3L Devices ), DDR2, or LPDDR1 SDRAM Devices Byte, short-word, word, long-word addressed ADDITIONAL FEATURES.
system crossbar and dma subsystem core 0 core 1 core 2 s peripherals 3× i2c 2× link ports 2× spi + 1× quad spi 3× uarts 3× epwm 8× timers + 1× counter 1× eppi adc control module (acm) async memory (16-bit) sd/sdio/emmc mlb 3-pin 2× can2.0 2× usb 2.0 hs mlb 6-pin pcie2.0 (1 lane) hadc (8 chan, 12-bit) 2× emac sinc filter 8x sharc ...
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