Transcription of SHARC Processor ADSP-21161N - Analog Devices
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SHARC Processor ADSP-21161N - Analog Devices
SHARC Processor ADSP- 21161n . SUMMARY Integrated peripherals integrated I/O Processor , 1M bit on- chip dual-ported SRAM, SDRAM controller, glueless multi- High performance 32-Bit DSP applications in audio, medi- processing features, and I/O ports (serial, link, external cal, military, wireless communications, graphics, imaging, bus, SPI, and JTAG). motor-control, and telephony ADSP- 21161n supports 32-bit fixed, 32-bit float, and 40-bit Super Harvard Architecture four independent buses for floating-point formats dual data fetch, instruction fetch, and nonintrusive zero- overhead I/O 100 MHz/110 MHz core instruction rate Code compatible with all other SHARC family DSPs Single-cycle instruction execution, including SIMD opera- tions in both computational units Single-instruction multiple-data (SIMD) computational archi- tecture two 32-bit IEEE floating-point computation units, Up to 660 MFLOPs peak and 440 MFLOPs sustained each with a multiplier, ALU, shifter, and register file performance Serial ports offer I2S support via 8 programmable and simul- 225-ball 17 mm 17 mm CSP_BGA package taneous receive or transmit pins, which support up to 16.
ADSP-21161N Rev. C | Page 3 of 60 | January 2013 GENERAL DESCRIPTION The ADSP-21161N SHARC® DSP is a low cost derivative of the ADSP-21160 featuring Analog Devices Super Harvard Archi-
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