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Simple and Correct Methodology for Verilog Include Files

Simple and Correct Methodology for Verilog Include Files Copyright 2008-2009 Karl W. Pfalzer 22-Sep-2008. Too many times I have seen the same problem with the Methodology related to the handling of Verilog Include Files . The simplest and Correct Methodology is identical to the one used for software development. (There are some further details at: ). The simplest Include file would look like: // // If we have not included file before, // this symbol _my_incl_vh_ is not defined. `ifndef _my_incl_vh_. `define _my_incl_vh_. // Start of Include contents `define N 4.

quick analysis of Verilog files. This analysis is limited to: whether all referenced modules (I.e., instances) are defined in the source file set all include search-paths are correctly defined no duplicate `defines are done no syntax errors (for implementation) are present supports Verilog IEEE Std 1364™-2005

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