Simple and Correct Methodology for Verilog Include Files

Simple and Correct Methodology for Verilog Include Files Copyright 2008-2009 Karl W. Pfalzer 22-Sep-2008. Too many times I have seen the same problem with the Methodology related to the handling of Verilog Include Files . The simplest and Correct Methodology is identical to the one used for software development. (There are some further details at: ). The simplest Include file would look like: // // If we have not included file before, // this symbol _my_incl_vh_ is not defined. `ifndef _my_incl_vh_. `define _my_incl_vh_. // Start of Include contents `define N 4. // Use parentheses to mitigate any undesired operator precedence issues `define M (`N << 2). `endif //_my_incl_vh_. Then, in any module where we need these definitions: // ` Include . module top(input clk, input [`N-1:0] in1, output [`M-1:0] q).

The `ifndef/`endif clause prevents redefinition (or inclusion) of the file's contents (if this same file was already included earlier). For example, another file m1.v also requires the N and M definitions, so the source for m1.v is:

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  Correct, Include, Verilog, Verilog include

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