Transcription of Simulating Verilog RTL using Synopsys VCS
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Simulating Verilog RTL using Synopsys VCS
Simulating Verilog RTL using Synopsys VCSCS250 Tutorial 4 (Version 091209a)September 12, 2010 Yunsup LeeIn this tutorial you will gain experience using Synopsys VCS to compile cycle-accurate executablesimulators from Verilog RTL. You will also learn how to use the Synopsys Waveform viewer totrace the various signals in your design. Figure 1 illustrates the basic VCS toolflow and RISC-Vtoolchain. For more information about the RISC-V toolchain consultTutorial 3: Build, Run, andWrite RISC-V takes a set of Verilog files as input and produces a simulator. When you execute the simulatoryou need some way to observe your design so that you can measure its performance and verify that itis working correctly. There are two primary ways to observe your design: (1) you can use$displaystatements in your Verilog RTL to output textual trace information, or (2) you can instruct thesimulator to automatically write transition information about each signal in your design to a is standard text format for this type of signal transition trace information called the ValueChange Dump format (VCD).
Sep 12, 2010 · CS250 Tutorial 4 (Version 091209a), Fall 2010 3 Getting started You can follow along through the tutorial yourself by typing in the commands marked with a ’%’ symbol at the shell prompt. To cut and paste commands from this tutorial into your bash shell
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