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Spartan-3AN FPGA Family Data Sheet (DS557)

DS557 June 12, Specification1 Copyright 2007 2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective 1: Introduction and Ordering InformationDS557 ( ) June 12, 2014 Introduction Features Architectural Overview Configuration Overview In-system Flash Memory Overview General I/O Capabilities Supported Packages and Package Marking Ordering InformationModule 2: Functional DescriptionDS557 ( ) June 12, 2014 The functionality of the Spartan -3AN FPGA Family is described in the following documents: UG331: Spartan-3 Generation F

† Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. † Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation.

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  Sheet, Data, Data sheet, Logic

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