Transcription of Spartan-6 FPGA Clocking Resources - xilinx.com
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Spartan-6 FPGA Clocking Resources - xilinx.com
Spartan-6 FPGA Clocking ResourcesUser GuideUG382 ( ) June 19, 2015 Spartan-6 FPGA Clocking ( ) June 19, 2015 DISCLAIMERThe information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of xilinx products. To the maximumextent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, xilinx hereby DISCLAIMS ALLWARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OFMERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE.
Spartan-6 FPGA Clocking Resources www.xilinx.com UG382 (v1.10) June 19, 2015 02/16/2011 1.5 Added BUFGMUX routing restrictions for DCM and PLL programming clock and BUFGMUX ASYNC usage to Clock Buffers and Multiplexers.
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