Standard Delay Format Specification - Sharif

1. Standard Delay Format Specification Version May 1995. Open Verilog International Contents 1 Introduction Introduction .. 1-1. Introduction to Version .. 1-1. Published by OVI .. 1-2. Acknowledgements.. 1-3. Version History .. 1-4. Version - June, 1993 .. 1-4. Version - February, 1994 .. 1-4. Correction to Version - July, 1994 .. 1-5. Version - April, 1995 .. 1-5. 2 SDF in the Design Process SDF in the Design Process.. 2-1. Sharing of Timing Data .. 2-1. Using Multiple SDF Files in One Design .. 2-1. Timing Data and Constraints .. 2-1. Timing Environment .. 2-1. Back-Annotation of Timing Data for Design Analysis .. 2-2. The Timing Calculator .. 2-2. The Annotator .. 2-3. Consistency Between SDF File and Design Description .. 2-4. Consistency Between SDF File and Timing Models.

The name of each SDF file is determined by the EDA tool. There are no conventions for naming SDF files. Version 3.0 of the Standard Delay Format includes many enhancements for the specification of the environment in which a circuit is operating with regard to timing. Along with existing and new constraint information, this

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  Standards, Specification, Delay, Format, Standard delay format specification, Standard delay format

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