Standard Gotchas: Subleties in the Verilog and ...

Standard GotchasSubtleties in the Verilog and systemverilog standards that every engineer Should Know!Don MillsMicrochipChandler, SutherlandSutherland HDL, , 20 LLHHDDSS uutthheerrllaannddtraining engineersto be systemverilog WizardsDon Mills,Don Mills,MicrochipMicrochipStu SutherlandStu SutherlandPresentation Overview What is a gotcha ? Why do standards have gotchas? What s covered in this paper Several example gotchas, and how to avoid them! Summary3of 20 LLHHDDSS uutthheerrllaannddtraining engineersto be systemverilog WizardsDon Mills,Don Mills,MicrochipMicrochipStu SutherlandStu SutherlandWhat Is A gotcha ?

Standard Gotchas Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know! Don Mills Microchip Chandler, Arizona don.mills@microchip.com

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