Summary of Verilog Syntax - Electrical Engineering …

Copyright 1997, Hon-Chi Ng. Permission to duplicate and distribute this document is herewith granted for sole educational purpose without any commercial advantage, provided this copyright message is accompanied in all the duplicates distributed. All other rights reserved. All Cadence s tools referred are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks belong to their respective owners. Summary of Verilog Syntax 1. Module & Instantiation of Instances A Module in Verilog is declared within the pair of keywords module and endmodule. Following the keyword module are the module name and port interface list. module my_module ( a, b, c, d ); input a, b; output c, d; .. endmodule All instances must be named except the instances of primitives.

Cpr E 305 Laboratory Tutorial Verilog Syntax Page 3 of 3 Last Updated: 02/07/01 4:24 PM d) z — high-impedance/floating state. Only for physical data types.

Loading..

Tags:

  Tutorials, Verilog, Tutorial verilog

Information

Related search queries